1. Field of the Invention
The disclosed apparatus and method relate to a data output circuit in a semiconductor memory and, more specifically, to a data output circuit, which is synchronized with a rising edge of a clock, that intermediately stores falling data up to next rising edge and merges final data based upon the stored falling data, thereby preventing failure among data and ensuring a wide range of operating frequency.
2. Description of the Related Art
A double data rate synchronous DRAM (hereinafter referred to as xe2x80x98DDRxe2x80x99) outputs two data for one period of the clock, while a conventional synchronous DRAM (hereinafter referred to as xe2x80x98SDRAMxe2x80x99) outputs only one data for one period. The DDR stores twice as much data as the conventional DRAM in parallel, and the stored data are arrayed in series in a following specific step. As a result, it is possible to output twice as much data as the conventional DRAM.
A circuit for converting parallel-data into serial data is called a data merging circuit. A conventional data output circuit for merging data is as shown in FIG. 1.
Referring to FIG. 1, when a clock CLK is inputted, a first core block 10 outputs rising data RDATA that is synchronized with a rising time point of the clock CLK and a second core block 20 outputs falling data FDATA that is synchronized with a falling time point of the clock CLK. The two data RDATA and FDATA are transferred to and stored in a rising data latch 30 and a falling data latch 40, respectively. The rising data latch 30 has inverters 31 and 32 to latch the data RDATA, and the falling data latch 40 has inverters 41 and 42 to latch the data FDATA. The rising data latch 30 and the falling data latch 40 latch the data RDATA and FDATA until a rising strobe switch 50 and a failing data strobe switch 60 are turned on.
Next, the data RDATA and FDATA from the rising data latch 30 and the falling data latch 40 are inputted to a data merging block 80. The data merging block 80 comprises the rising data strobe switch 50 and the falling data strobe switch 60. The rising data strobe switch 50 includes a transfer gate 51 and an inverter 52, and the falling data strobe switch 60 includes a transfer gate 61 and an inverter 62. The rising data strobe switch 50 allows the data stored in the rising data latch 30 to pass through a merged data latch 70 having inverters 71, 72 when a rising data strobe signal RSTB is enabled. Also, the falling data strobe switch 60 allows the data stored in the falling data latch 40 to pass through a merged data latch 70 when a falling data strobe signal FSTB is enabled. In this case, the rising data strobe signal RSTB is generated as synchronized with the rising edge of the clock CLK, and the falling data strobe signal FSTB is generated as synchronized with the falling edge of the clock CLK.
In a common DDR product, a Delay Locked Loop (DLL) circuit is used to generate the rising data strobe signal RSTB before a predetermined time interval tPB starting at the rising edge of the clock CLK and to generate the falling data strobe signal FSTB before the predetermined time interval tPB starting at the falling edge of the clock CLK. As shown in FIG. 2, the rising data strobe signal RSTB and the falling data strobe signals FSTB have the pulse widths that are substantially identical to tPB.
Also, the merged data latch 70 stores a data merged signal CDATA, which is merged in series through the above-described operations of the rising data strobe switch 50 and the falling data strobe switch 60 of the data merging block 80.
An operation process of the conventional data output circuit as configured above will be described with reference to FIGS. 2 and 3.
The first core block 10 and the second core block 20 each output the rising data RDATA and the falling data FDATA at a predetermined time interval tPA starting at a rising edge time point t0 of the clock CLK. The outputted RDATA and FDATA are respectively stored in the rising data latch 30 and the falling data latch 40. In this case, the rising data latch 30 maintains the stored signal until the rising data strobe signal RSTB is enabled, and the falling data latch 40 maintains the stored signal until the falling data strobe signal FSTB is enabled.
The rising data strobe signal RSTB is enabled at the time interval tPB ending at a time point t2. At this time, the rising data strobe switch 50 is turned on and then the rising data RDATA stored in the rising data latch 30 is outputted into the merged data latch 70. The merged data latch 70 outputs the final data merged signal CDTA of a logic high level, based upon the rising data RDATA.
When the falling data strobe signal FSTB is enabled at the time interval tPB ending at a time point t3, the falling data strobe switch 50 is turned on, thereby outputting the falling data FDATA stored in the falling data latch 40 into the merged data latch 70. The merged data latch 70 outputs the final data merged signal CDATA of a logic low level, based upon the falling data FDATA.
As a result, the parallel data RDATA and FDATA are produced in the first and second core blocks 10 and 20, as synchronized with the rising edges of the clock CLK such as the time points t0 and t2, whereas the data merged signal CDATA is generated from the merged data latch 70, as synchronized with both of rising and falling edges of the clock CLK such as time points t2, t3, t4 and t5.
Like this, the data RDATA and FDATA which were respectively produced in parallel in the first and second core blocks 10 and 20 are merged to be the serial data merged signal CDATA, accordingly enabling the operation at a double data rate.
FIG. 3 illustrates the data flow related to the times and signals occurring in the above-described operation.
The rising data RDATA and the falling data FDATA generated by the first and second core blocks 10 and 20 at the rising edge of the clock CLK are outputted into the data merging block 80 after the time tPA. These data RDATA and FDATA are respectively latched by the rising data latch 30 and the falling data latch 40. With a delay of the time tPB, data RDATA and FDATA are outputted as the data merged signal CDATA by the merged data latch 70.
In case that one period tCK of the clock CLK is smaller than the fixed delay times tPA and tPB, the conventional data output circuit has no problem in data transmission and mergence as shown in the timings of FIG. 2. However, if the one period tCK is larger by a large margin than the fixed delay times tPA and tPB, there is a problem that data failure may take place as shown in timings of FIG. 4 and a graph of FIG. 5.
Referring to FIGS. 4 and 5, if the falling data strobe switch 60 is turned on, new data is input into the falling data latch 40 at the time point t3 when the falling data FDATA stored in the falling data latch 40 is not yet outputted into the merged data latch 70. Accordingly, the previously stored falling data (C) disappears resulting in data failure.
Correlation between the period tCK of the clock signal and data failure is described in detail as follows.
The first data generated from the second core block 20 is stored in the falling data latch 40 up to activation of the falling data strobe signal FSTB. Here, FSTB is activated after a time of 1.5 tCKxe2x88x92tPB starting at the generation of the first data from the second core block 20. Also, the second data is generated from the second block 20, and then transferred into the falling data latch 40 after a time of tCK+tPA starting at the generation of the first data. Further, since the second new data should be inputted after the first data is outputted to the merged data latch 70, an equation is realized as follows:
1.5tCKxe2x88x92tPB less than tCK+tPAxe2x80x83xe2x80x83(1)
Equation 1 is arranged about tCK as follows:
tCK less than 2(tPA+tPB)xe2x80x83xe2x80x83(2)
In other words, one period tCK of the clock CLK is necessarily smaller than 2(tPA+tPB) in order to avoid generation of failed data and, thus, there is an upper limit of tCK due to the features of the data merging circuit. As a result, the conventional data output circuit may not operate normally in a low frequency range and, thus, a product employing the circuit has a heavy restriction in performance.
Accordingly, the disclosed device and method have been proposed to solve the foregoing problems.
The disclosed device and method provide a data output circuit in a semiconductor memory that intermediately stores falling data that is synchronized with a rising edge of a clock up to the next rising edge and merges final data based upon the stored falling data. As a result, it is possible to prevent failure between data and to ensure a wide frequency range.
According to the teachings of the disclosed device, there is provided a data output circuit in a semiconductor memory having a rising data latch for latching a rising data that is inputted in synchronization with a clock. Further included is a falling data latch for latching a falling data that is inputted in synchronization with the clock. A rising data strobe switch is included for outputting the rising data in synchronization with a rising edge of the clock into an output node in response to a rising data strobe signal. A delay means delays the failing data for a predetermined time period in response to the rising data strobe signal. Finally, a first falling data strobe switch is included for outputting the delayed falling data, as synchronized with a falling edge of the clock into the output node, in response to a falling data strobe signal.
According to the teachings of the disclosed device, there is provided a data output circuit in a semiconductor memory having a rising data latch for latching a rising data that is inputted in synchronization with a clock. Further included is a falling data latch for latching a falling data that is inputted in synchronization with the clock. A rising data strobe switch is included for outputting the rising data in synchronization with a rising edge of the clock into an output node in response to a rising data strobe signal. A delay means or delay circuit delays the falling data for a predetermined time period in response to the rising data strobe signal. Finally, a first falling data strobe switch is included for outputting the delayed falling data, as synchronized with a falling edge of the clock into the output node, in response to a falling data strobe signal.